Accessing inputs and outputs of a custom component

You need to take care of address in your custom component.Address will be as shown in below code.

//RTL Code for write logic

case({av_write,av_address[4:0]})

6'b1_00000 cipher_in1[31:0] <= av_wrdata;

6'b1_00100 cipher_in1[63:32] <= av_wrdata;

6'b1_01000 cipher_in1[95:64] <= av_wrdata;

6'b1_01100 cipher_in1[127:96] <= av_wrdata;

6'b1_10000 cipher_in2[31:0] <= av_wrdata;

6'b1_10100 cipher_in2[63:32] <= av_wrdata;

6'b1_11000 cipher_in2[95:64] <= av_wrdata;

6'b1_11100 cipher_in2[127:96] <= av_wrdata;

endcase

//RTL code for read logic

case(av_address)

0 : av_rddata <= cipher_out[31:0];

4 : av_rddata <= cipher_out[63:32];

8 : av_rddata <= cipher_out[95:64];

12 : av_rddata <= cipher_out[127:96];

endcase

//NIOS Code

//Cipher Input 1

IOWR(CIPHER_0_BASE,0x00,0x03020100);

IOWR(CIPHER_0_BASE,0x04,0x07060504);

IOWR(CIPHER_0_BASE,0x08,0x0b0a0908);

IOWR(CIPHER_0_BASE,0x0c,0x0f0e0d0c);

//Cipher Input 2

IOWR(CIPHER_0_BASE,0x10,0x03020100);

IOWR(CIPHER_0_BASE,0x14,0x07060504);

IOWR(CIPHER_0_BASE,0x18,0x0b0a0908);

IOWR(CIPHER_0_BASE,0x1c,0x0f0e0d0c);