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SSchm28's avatar
SSchm28
Icon for New Contributor rankNew Contributor
5 years ago

Video and Image Processing Suite - can't fit design / can't read "fifo_type": no such variable

Hello, I have two projects with an Cyclone 10lp16k FPGA using the VIP ip cores from intel. I develop with the Quartus Prime Lite 20.1 version (Windows). In the first project, compilation and fit...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Sebastian,


I wouldn't advise you to remove the sdc constraint else I worry it may impact the VIP functionality.


I looked the sdc file constraint as per attachment. Looks like it's detecting data input to decide whether it should perform additional timing constraint for DCFIFO or not.


I know you are seeing fitter error due to the nature of how the SDC constraint file is written but since after providing user logic data input to the VIP suite IP then the fitter error will be gone.

  • In your actual project development, I do expect you will be supplying data to VIP suite IP to process the video data accordingly as well


I know it's not perfect but do you still a problem while working on your actual Quartus design development when you supply actual video data to VIP suite IP ?


Thanks.


Regards,

dlim