RX Mac segmented interface detailed information

I am using Ftile ethernet hard IP (400G configuration) . I complied the example test design with signal tap to monitor RX mac segmented interface and loaded on MA2700 . The kit is connected to a host with 400G capable NIC in it. I am using ping command and via wireshark I can see that host sends ARP request packet to the kit. As the ARP request packets are sent to the kit, I triggered STP and capture I have attached screenshot.

you can see all data in the capture other than rx_mac data.

rx mac data on clock -1 and 0 are as following

-1 -> E39001000406000801000608AAEB6A17E390FFFFFFFFFFFFD5555555555555FB070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707

0 -> 070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707070707FDE831AB370000000000000000000000000000000000006501A8C0000000000000C801A8C0AAEB6A17

From wireshark I can see this ARP packet is 60bytes and all the fields matches with what I see in the o_rx_mac_data.

Now I am trying to make sense of Rx mac segmented interface and I have following questions.

1. rx mac inframe values are E000h and 000Fh meaning total 7 bits are 1 (logic high) indicating 56 byte packet but from payload is 60 bytes. So how do I equate for remining 4 bytes?
2. in user guide o_rx_mac_eop_empty [47:0] signal is explained as "Indicates the number of empty bytes on the RX data signal, starting from the most significant byte (MSB). Valid only on EOP segments." I dont understand this statement completely so please help; as per signal tap waveform clock 0 is where packet ends and the value of bus is 4800h. I am not sure if and how this value can help equates for missing 4 bytes.
3. Figure 44. Receiving Data Using the RX MAC Client Interface is little help- and small explanation below it (has typos i think) is not much help. Do you have more details and example for MAC segmented interface which you can share with me so that I can learn exact details on how to use this interface to receive incoming packets from Ftile.
4. Using above signaltap screenshot and o_rx_mac_data values for clock -1 and 0; how do i detect sop? how do i use rx mac_sengemented interface to detect eop ? how do i use rx mac_sengemented interface detect exact length of ethernet frame which is being supplied during clock -1 and 0.