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Altera_Forum
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10 years ago

FFT Megacore sink_ready never goes to 1

Right now I am trying to read 16 bit values from memory and put the data into the FFT Megacore function I have in my design. The only problem is that in my Verilog project, the sink_ready value never...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi Behrazv,

Yes, this is important to issue an reset to the IP at the beginning of the simulation or when you power up the device.

If the sink_ready signal becomes don't care (Stx) in simulation, it could be due to certain library files was missing. Assuming you are using Model-sim to run the simulation, you may refer to the simulation script "msim_setup.tcl" that generated by the IP for all of the necessary simulation files.

Best Regards,

Terence

(This message was posted on behalf of Intel Corporation)