XAUI Phy in Stratix IV GX

Dave, you are right. The bytes are swapped. Also in some cases the alignment is not correct.

I read in the transceiver section of Stratix IV hadbook that byte ordering is disabled in XAUI mode (refer figure 1-123, page 1-156). Furthermore the rx_enabyteord (together with rx_

byteorderalignstatus) signal is just used when byte ordering block is enabled. In XAUI mode I don't have access to these signals.

Even if I had the possibility to restart byte ordering operation how should I know when it is to do?

After each reset the byte order is random. In the attached screenshots you see also the misalignment. Affected are also the control signals.

Transmit:

control | 0xFF | 0x00

lane 3 | 0x0707 | 0xAD00

lane 2 | 0x0707 | 0x0000

lane 1 | 0x0707 | 0x0000

lane 0 | 0x0707 | 0x00AB

Receive:

control | 0xFF | 0x55 | 0xAA

lane 3 | 0x0707 | 0x0007 | 0x07AD

lane 2 | 0x0707 | 0x0007 | 0x0700

lane 1 | 0x0707 | 0x0007 | 0x0700

lane 0 | 0x0707 | 0xAB07 | 0x0700

(for more details see signal tap files in the zip archive).

Dave, you have an example with XAUI running on the Devkit and loopback adapter? I could compare it with my implementation.

Jens

Jens