Wit's end: Cyclone III PLLs lose lock when more than one FPGA connected?

Is the base clock wave somehow affected by the insertion of more than one board?

I mean, do you observe any change in duty cycle, level or wave shape compared to the case when you have one single board?

Does the base clock travels a long path in the backplane? Do you use any termination on the trace?

Another guess: is possible that the big bulk capacitance is actually the reason of the problem? The added capacitance could slow down the power supply risetime and prevent correct resetting of the PLL circuitry.