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Altera_Forum
Honored Contributor
Honored ContributorWith the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA?
Hello everyone, I want to make something that records values that are in my FPGA. I thought of using the Cyclone V SoC DMA, I do have the Altera SoC kit. With the Cyclone V SoC, how can I ...
Altera_ForumHonored Contributor
Honored ContributorThe F2S interfaces expose a 4GB address space so if your DMA is limitted in it's addressing capabilities you might need to put that address span bridge between it and the HPS. The DMA and SGDMA in Qsys only support up to 4GB but the mSGDMA up on alterawiki.com supports up to 64-bit addressing if you enable the enhanced descriptors. So if you used the mSGDMA you wouldn't need the address span bridge.
Regardless of the DMA addressing capabilities you might want to expose only a subset of the full 4GB SDRAM range so that the addressing logic in the DMA is not as wide. That typically drops the Fmax of the design when you try to master lots of memory so you might want to limit the address span using the address span bridge. For example lets say you only want to make addresses 0x1000_0000 to 0x100F_FFFF (1MB window) available you could setup the address span bridge to expose a 1MB range and have it hardcoded to start at 0x1000_0000.
