With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA?

Actually I have a design planned to do exactly this but unfortunately it's not ready yet. You don't necessarily need to fence off a region of memory for the FPGA to access, you could dynamically allocate some space and pass the location to the FPGA logic to access later.

I think if you look at the golden hardware reference design there is a connection between some FPGA logic and the HPS SDRAM that you can take a look at. If I remember correctly there is a JTAG-to-Avalon memory mapped bridge connected which lets you peak and poke memory using system console. You'll want something more self contained but it would be a good starting point to look at to see how to configure the memory controller to give the FPGA access to it.