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Altera_Forum
Honored Contributor
Honored Contributorwill add a module or IP change the performance? (combining SDI and SGDMA)
Hi all I'm wondering whether adding a module or an IP to an FPGA design can change the performance. From what I know, I guess the performance would be changed because different place and rout...
Altera_ForumHonored Contributor
Honored ContributorHi Aphraton
If I remember right, opening a qsys file and clicking "system" --> "Insert avalon-st adapter" will automatically add some avalon-st adapters in the qsys design. (You don't need to do this if there's no error or warning related to the avalon-st interface.) For the DC FIFO, I use it between two components working under different clock frequency.
