Wierd Fifo RdReq problem

Hi Rysc,

Well i am observing this problem through both signal tap and simulink simulation.

Well I have put logic in there to prevent the fifo from hitting its thresh hold.

It makes sure not to allow to write to it if almost full and not to read from it when almost empty.

This particular fifo has a with of 512 words of 8 bits and is set to be a show ahead fifot.( mind you i changed it to be a show ahead fifo thinking it might solve the problem).

The unusual thing is this fifo works fin with any other block except the scaler block. It seems the problem occurs when the scaler requests for data in burst mode and then suddenly switch to continuous mode( 1 byte at a time), causing the fifo to miss one read request.

I have tried my block with other blocks and they work fine.

hope to hear from you soon.

regards Nadeem