Wierd Fifo RdReq problem

Hmmm. A few more questions... Is this in simulation or in SignalTap? How deep is the FIFO and what are the usedwords at(is it near a thresh-hold, full or empty)? Do you see the rdreq actually strobing(or is it just held high and you're streaming). My initial guess is that you've hit a full/empty threshold and the the rdreq or wrreq is ignored. Note that if you're even near the threshhold's the flag's can "act funny" in an asynch FIFO, because they need to be pro-active. (An example is that you might be approaching empty, but not really quite there yet, and the wrempty flag goes high for a clock or two. If you do a read, it will be ignored. But even if you don't do anything, a clock or two later the empty flag would then go low, and that's because the rdpointer and wrpointers have synched up.) Also make sure you're using the right domain pointer, i.e. the rdempty flag to stop reads because the FIFO is empty and the wrfull flag to stop writing because it is full.