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Altera_Forum
Honored Contributor
18 years agoWierd Fifo RdReq problem
Hello All, How are you? I am kinda new to altera and FPGA's so mind me for my simple mindedness. Anyways I am designing a Colorization Unit for a 12bit gray scale video feed. Basicaly this...
Altera_Forum
Honored Contributor
18 years agoThanks Rsyc for your reply.
Well I have got buffer overflow and underflow protection, but at the same time i have made in built protection, so the module does not messup. Well its Odd as this messup happens some around 4000 reads. But mind you it only happens once and does not occur again. Yes it seems the mess up happens exactly at the same place every time which i find very odd. The fifo is running in Async mode. hope to hear back from you , regards Nadeem