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Altera_Forum
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18 years ago

Wierd Fifo RdReq problem

Hello All, How are you? I am kinda new to altera and FPGA's so mind me for my simple mindedness. Anyways I am designing a Colorization Unit for a 12bit gray scale video feed. Basicaly this...
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Altera_Forum
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18 years ago

Does the "mess-up" always occur in the same manner? Is it always the first read after configuration/reset? What has happened to the FIFO(have there been a good number of writes to the FIFO, i.e are you sure data is in it and it's not empty)? Is it synchronous or asynchronous?