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AWrithingMassOfFlesh's avatar
AWrithingMassOfFlesh
Icon for Occasional Contributor rankOccasional Contributor
6 years ago
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Why would these two clear on reads behave differently?

Device: Cyclone IV EP4CE15F17C8N HDL: Verilog We have a register (status_reg) in our FPGA that we want to clear when we read (IE push data it to SPI buffer). When we read this register, we & it wit...
  • ak6dn's avatar
    ak6dn
    6 years ago

    Well, that looks basically ok.

    I would have to assume that input CS is only valid for a single clock cycle. Correct?

    Or if CS is valid for more than one clock cycle then SPI_RD is only valid for one clock cycle.

    Otherwise if CS and/or SPI_RD is present for two (or more cycles) the register will be read once, then cleared, then read again with the value zero.

ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
6 years ago

I have come across this kind of problem before.

The way I handled it was to basically design a 'positive edge' detector to qualify the use of the signal, so that it is only qualified the first clock period it goes high.

So, register the signal to delay it one clock: always @(posedge clk) csd1 <= cs;

then whenever you use cs later, use: cs & ~csd1 instead.