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AWrithingMassOfFlesh's avatar
AWrithingMassOfFlesh
Icon for Occasional Contributor rankOccasional Contributor
6 years ago
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Why would these two clear on reads behave differently?

Device: Cyclone IV EP4CE15F17C8N HDL: Verilog We have a register (status_reg) in our FPGA that we want to clear when we read (IE push data it to SPI buffer). When we read this register, we & it wit...
  • ak6dn's avatar
    ak6dn
    6 years ago

    Well, that looks basically ok.

    I would have to assume that input CS is only valid for a single clock cycle. Correct?

    Or if CS is valid for more than one clock cycle then SPI_RD is only valid for one clock cycle.

    Otherwise if CS and/or SPI_RD is present for two (or more cycles) the register will be read once, then cleared, then read again with the value zero.

AWrithingMassOfFlesh's avatar
AWrithingMassOfFlesh
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

So it looks like SPI_RD was high for too many cycles, and the data were being read, then cleared, then read again like you described.

We added logic to only clear status_reg after the register had been read by the SPI.

To do this, we separated the two operations into two SPI commands.

Since status_reg is continuously updated, we added status_temp to preserve any new statuses that come in during the time after we read the status_reg but before we clear it.

//during read

begin data_out <= status_reg[15:0]; status_temp[15:0] <= status_reg[15:0]; end

//after read

status_reg <= (status_reg[15:0] ^ status_temp[15:0])|(status_reg[15:0] & 16'b1110000000110001);

Thanks for your help!