BQi
Occasional Contributor
Occasional Contributorwhy we can not generate pcie ep ipcore example design?
we use below ip config, but we can not generate pcie ep ipcore example design, pls help
Forum Discussion
BoonT_Intel
Frequent Contributor
Frequent ContributorHi Sir,
What is the IP that you using and what FPGA device?
Based on the IP file that you attached in this thread early. I am open it with Quartus 19.4 and it give me Avalon-MM Intel S10 Hard IP for PCIe.
And based on this IP, the Avalon-MM setting tab is looks like this screenshot.
It is different from your screenshot. And the parameter that I mentioned is the “Address width of accessible PCIe memory space” as highlight in yellow. You should set it to 62 or below.
