Why is the use of different PLL feedback modes in Altera devices?

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The documentation states that the Altera PLLs have 6 different clock feedback modes. These are:

1. Direct mode

2. Normal mode

3. Source-Synchronous mode

4. External Feedback mode

5. Zero-Delay Buffer mode

6. LVDS mode

Why are there so many clock feedback modes and how do I know which one I need?

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They are offered to tackle timing problems in case you have io violations.

Direct : only de-jitters clock, does not compensate for delay.

normal, de-jitters and reduces clock delay from pin to register and compensates for clock delay from pin

source synchronous, keeps data/clk phase same between pins and registers

external: relevant if so

zero delay: relevant to an output clock from pll, maintains same phase of output clock as that of input clock.

lvds: relevant to serdes.