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Altera_Forum
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14 years ago

Why is Altera force-feeding us with Verilog?

Altera definitely (?) is using Verilog (and System Verilog) to build their latest IP. That's fine by me, after all it is IP and most users don't want to see the internals anyway. But the accompan...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

i think the memory controllers (and most of the IP) are developed internally

josby: i can sympathize, i recently had to jump from VHDL to Verilog. its not hard at all