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Altera_Forum
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14 years ago

Why is Altera force-feeding us with Verilog?

Altera definitely (?) is using Verilog (and System Verilog) to build their latest IP. That's fine by me, after all it is IP and most users don't want to see the internals anyway. But the accompan...
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Altera_Forum
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14 years ago

The only "nice" way would be to write the examples twice. This can get really expensive(not just time writing both, but time spent debugging the two, ensuring equivalency, hiring engineers who are good at both, etc.) It's an ugly problem for IP development. I know it's painful to you and that doesn't help, just mentioning for some sympathy.