--- Quote Start ---
Generated code, from just about anywhere, is pretty poor. I am a bit dissapointed with non-standard VHDL though. It was probably provided by an external contractor (as I think they produce most of the IP).
How about raising a support request? You wont achieve alot ranting about it on this forum.
--- Quote End ---
I do not fully agree with the fact that generated code has to be ugly and illegible, but if you start off with something poorly readable it won't get any prettier translating it.
Looks like they assign the job to the lowest bidder ...
The SR: I am just a poor boy (one of the 80% of the customer base only generating 20% of the revenue) ... and I really don't think Altera will answer anything else than a polite 'this is the way things go down'.
I just wanted to get this off my chest. I started using AHDL back in '93 (coming from PALASM and Abel). At some point it looked like Altera was going to switch to VHDL, and we finally went along. Now they have switched to this other language and are orphaning the VHDL user. So I'll just have to learn to read Verilog and its siblings (better than I do now). You never know, but I might even start liking it:)
Honored Contributor
