New ContributorWhy Arria 10 Transceiver calibration fail whenever PCIe hard IP core is added to the design?
More information about your specific scenario would be helpful (is it the PCIe A10 GXB that is failing - or another?). For what it's worth, If you have PCIe + any other GXBs that are being used, there is a cascading of cal_done signals that requires that any PCIe hard IPs have to be running and calibrate OK (i.e. connected to a PCIe master) and then the cal_done signals are propagated downstream to any other GXBs that might be used and then their calibrations are attempted. So, if you have a hard PCIe GXB that is in a design - and then another that is being used for, say, CPRI or some other function, the CPRI core GXB will not attempt to start calibration until the PCIe hard IP GXB has successfully calibrated. This is due to requirement for CVP (config via protocol) where PCIe needs to be a the default / first interface configured.
Bottom line: In a design that uses PCIe GXBs + anything else, you need a PCIe reference clock that's valid before any of the other GXBs can calibrate.
Refer to section 7.3 (page 582) of the following doc:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf
Based on your title and lack of info, this is an educated guess on what might be happening. I've seen this in practice - no other GXBs calibrate if a PCIe core is used in design - but doesn't happen to be connected.
Jeff
