What's wrong with the modelsim

Question

i have transfer the block symbol file to the verilog using quartus,but i simulate it in the modelsim,it has the wrong answer.

this is the block file of a three ffs.

the is the modelsim result,

but when i write the verilog myself ,i get the right answer,so what's wrong with the Modelsim,any ideas? Many thanks!

altera_forum · Answer

are you converting the .bdf to Verilog? can you post the converted Verilog?

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