What's the parameter 'pfd_clk_select'?

Question

Today, I built a new QuartusII project. The project include two ALT2GXB block, I don't assign the pins. When I compile this project. Quartus point out a error :

Error: WYSIWYG primitive "channel_quad[0].pll0" has CLK[2] port that must be connected because parameter pfd_clk_select is set to 2

What's the parameter pfd_clk_select? How to solve it?

Thank you!

altera_forum · Answer

If the ALT2GXB pll_clk port miss source or has a wrong source, Quartus will show this error.  But I don't know what's the parameter pfd_clk_select mean?

Forum Discussion

What's the parameter 'pfd_clk_select'?

1 Reply

Recent Discussions

Agilex 7 R-Tile RBES FPGA – Board Fails to Power On and JTAG Not Detected

Agilex 7 R-Tile RBES FPGA – CXL Device Enumeration Failure with CXL IP Design Example

Agilex 7 R-Tile RES FPGA – CXL Device Enumeration Failure with CXL IP Design Example

MAX10 FPGA pof-file programming fails

Arria 10: Remote Update Watchdog unpredicted behavior