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MinzhiWang
Occasional Contributor
Occasional ContributorWhat's the internal tS and tH value of the resister inside FPGA?
Hello Guys, We have one application to detect pulse or its rising edge. So two FFs are used to implement this function. The function diagram as following. We have to know the register's tS and tH pa...
sstrell
Super Contributor
Super Contributor1000 ps = 1 ns which should be fine. What's the clock frequency? Yes, setup and hold times can vary. The most accurate info would be from the timing analyzer in Quartus, though you would need to create a design (could be as simple as this diagram) and run an analysis. There is a datasheet report in the tool (I forget the command) that would include setup and hold time info.
