What's the internal tS and tH value of the resister inside FPGA?

1000 ps = 1 ns which should be fine. What's the clock frequency? Yes, setup and hold times can vary. The most accurate info would be from the timing analyzer in Quartus, though you would need to create a design (could be as simple as this diagram) and run an analysis. There is a datasheet report in the tool (I forget the command) that would include setup and hold time info.