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Altera_Forum
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13 years ago

What the relative timing relations between 2 clocks out of the PLLs？

Hi all: I have a question about PLL’s output clocks. In my project, the input clock is 100MHz. I generate a 387.5MHz clock using PLL with multiplying/dividing factor of (32/8), and anothe...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Hi FvM&jimbo:

Thanks for you reply!

I want to emulate random “HITs” for my system, instead of analyzing these clocks. PLL will generate a low speed clock as the HITs(pulse’s edges), and a high speed clock to check the relations between HITs and the closest edge of the high speed clock. So I want to get as much as possible relations between the low speed clock’s edge and high speed clock’s edge. For example, there is only one possibility phase relation between 25MHz clock 250MHz. However, there may be many possibilities between 250MHz and 31.234565789MHz. My question is that I must find a way to know how many possibilities in this example. I just mean discussing it theoreticly, and skip the clock skew, jitter and so on.