What the relative timing relations between 2 clocks out of the PLLs？

Minor point but I think you meant to say (31/8) to get 387.5 MHz from 100 MHz input clock. Also, (32/19) for an input clock of 20 MHz yields a ~33.68 MHz output clock. If you have a clock crossing between the 387.5 MHz clock and the 33.68 MHz clock, you cannot time this accurately in TimeQuest as you will most likely get a 1 ps Setup Relationship since they are not integer multiples of each other. You will have to synchronize this clock crossing and then create a false_path constraint between the clocks.