What memory to choose SRAM or SDRAM?

I have two questions regarding DRAM/SDRAM and hopefully somebody in this forum can help me. I tried them with Micron and another manufacturer but they would not go into detail since they claimed confidentiality.

Question# 1. If for some reason I can store the row address and if there is a row hit and I would be able to retrieve the row right away. Can I cut down on the number of tRCD clock cycles (typically 2 clocks) or better yet can I completely eliminate it. What I meant was can I skip the Ras cycle and retrieve row addresses from the register, decoded them at the same time column addresses are selected.

The second question is if I am at the same row addresses but need access to different bank. Can I just decode the bank at the same time I decode column address since the new bank is valid during the entire cycle (both Ras & Cas). It looks like in the datasheet that it still takes tRCD cycles. My argument is you do not have to reload the row address since it is the same and bank and column addresses can be decoded at the same cycle and therefore you can shave one or get rid of tRCD cycles completely.

Thank you very much for any response.

Regards,

SML