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Altera_Forum's avatar
Altera_Forum
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10 years ago

what kind of refclk standard do alt2gxb need?

I use ArriaGX in a PCIe design, and use ICS9DB403 to generate 100MHz refclk for alt2gxb. But GXB cannot receive any refclk signal. ICS9DB403 generate a HSCL standard signal. I wonder if alt2gxb cou...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi,

This question is regarding the PCIe HSCL REFclock (of Transceiver bank) to FPGA (STX5). The 100MHz clock is sourced from IDT HSCL buffer and we have "DC COUPLED" the clock.

Below is the topology used:

TX - R(pull down) - R(series) - 2 inch trace - RX

At RX (ie. FPGA), we have done the following settings in FPGA QSF file:

set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION DC_COUPLING_EXTERNAL_RESISTOR

Below is the setting in FPGA PIN file:

refclk0_pcie(n) : W5 : input : HCSL : : B0R : Y

refclk0_pcie : W6 : input : HCSL : : B0R : Y

Below are my queries:

1. In my case as well, I need to provide an external 100 ohms termination between P and N?

2. Considering my case (DC coupling to FPGA), if I enable internal 100 ohms, it will also enable internal biasing. Is this understanding correct?

If so, then is it still OK to use internal termination and biasing settings for this "DC COUPLED" clock?