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Altera_Forum
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14 years ago

What is the processing speed limitation of Cyclone IV E with speed grade C7?

Hi everyone, Does anyone know, what is the maximum processing speed of Cyclone IV E (with speed grade of C7) within the FPGA fabric? Knowing that PLL on Cyclone IV E can generate up to 1....
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Altera_Forum
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14 years ago

One usually uses "MHz" for clock frequencies and "Mbps" for data rates.

In the case, the LVDS receiver uses DDR, so the data rate (per pin) is twice the clock frequency.