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Altera_Forum
Honored Contributor
Honored ContributorWhat is the processing speed limitation of Cyclone IV E with speed grade C7?
Hi everyone, Does anyone know, what is the maximum processing speed of Cyclone IV E (with speed grade of C7) within the FPGA fabric? Knowing that PLL on Cyclone IV E can generate up to 1....
Altera_ForumHonored Contributor
Honored ContributorOne usually uses "MHz" for clock frequencies and "Mbps" for data rates.
In the case, the LVDS receiver uses DDR, so the data rate (per pin) is twice the clock frequency.
