What is the processing speed limitation of Cyclone IV E with speed grade C7?

Hi Dave,

I've always wanted to ask what's the difference between MHz and Mbps in LVDS? Since LVDS is basically in binary, which is on and off per unit time, so i thought using MHz to describe Mbps here would be the same?

Could you elaborate a little more on how you get 105MHz?, and what is setup/hold time of the receivers?

"Adding an external clocked multiplexer..." i wanted to make this in the FPGA using verilog. If this does not work, do you think it will work if i use a discrete deserializer chip?

And how could one overclocks the FPGA? cool down the FPGA? increase core voltage? this is getting interesting!.

Thanks!

Regards,

Michael