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Altera_Forum's avatar
Altera_Forum
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15 years ago

what causes Verilog error?

I have another error when compiled with Quartus II: if (Data_Lmt == 0) begin CS1reg <= 1'b1; CS2reg <= 1'b1; Databus <= SPIdata_reg; // Error (10137): V...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Databus has to be inout type. The statement Databus <= SPIdata_reg; must be within that if loop and the if is within the always block...

In this case, how could I fix this error? Thanks.