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Altera_Forum
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14 years ago

what causes Verilog error?

I have another error when compiled with Quartus II: if (Data_Lmt == 0) begin CS1reg <= 1'b1; CS2reg <= 1'b1; Databus <= SPIdata_reg; // Error (10137): V...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Use (outside of any always blocks):

assign Databus = SPIdata_reg;

If it really needs to be a bidirectional inout signal type, you should have some sort of output enable signal and declare it as:

assign Databus = output_enable? SPIdata_reg: 8'bz;

if not, declare Databus as an output and use the simpler first assignment statement.