what causes Verilog error?

Use (outside of any always blocks):

assign Databus = SPIdata_reg;

If it really needs to be a bidirectional inout signal type, you should have some sort of output enable signal and declare it as:

assign Databus = output_enable? SPIdata_reg: 8'bz;

if not, declare Databus as an output and use the simpler first assignment statement.