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Altera_Forum
Honored Contributor
Honored ContributorWhat can I do if I come across following question?
Error: Can't generate netlist output files because the file "E:/2008-04-01/DDR_71/auk_ddr_hp_controller.vhd" is an OpenCore Plus time-limited file
Altera_ForumHonored Contributor
Honored ContributorI have used my workmate's computer to compile ,it is success,How can to know the relatives between the PLL frequency and memory frequency.
