Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Voltage level problem on a pin which is a clock

Hi all, I create this thread because I have a debug problem. On my PCB, my FPGA (EP3C5E144C8N) has to generate a clock to a PHY chip (Marvell 88E1111). With my scope, I can see th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi hinanotabu86,

Actually the use of a VREF pin could be the problem.

VREF pins have a higher capacitance than normal pins.

With a frequency of 125MHz this certainly has (some) impact.

From the Cyclone III handbook: When VREF pins are used as regular I/Os, they have higher pin capacitance than

regular user I/O pins. This has an impact on the timing if the pins are used as inputs

and outputs.

From the Cyclone III datasheet:When VREF pin is used as regular input or output, a reduced performance of toggle rate and tCO is expected due to higher pin capacitance.

The capacitance of the VREF pin is 21 or 23 pF. For a normal pin it's about 6 pF.

Just route your output to another pin, and measure again. Just to be sure

Good luck, Ton