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Altera_Forum
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15 years ago

Voltage level problem on a pin which is a clock

Hi all, I create this thread because I have a debug problem. On my PCB, my FPGA (EP3C5E144C8N) has to generate a clock to a PHY chip (Marvell 88E1111). With my scope, I can see th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

lots of people told me about an impedance adaptation

considering that i can't recompile my project (because of a licence of one particular IP I bought), does someone know how to adapt impedance without an operationnal amplifier