Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Voltage level problem on a pin which is a clock

Hi all, I create this thread because I have a debug problem. On my PCB, my FPGA (EP3C5E144C8N) has to generate a clock to a PHY chip (Marvell 88E1111). With my scope, I can see th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

thanks std_logic_vector

incrdible similarity, in my case the clock is a nice sinusoide but with bad voltage level

i checked pin planner, my clock pin is 2.5V (no suffix), nothing concerning LVDS (a colleage suggest me that)

the corresponding bank has a correct voltage supply VCCio to 2.5V / GND to 0V, and I have separate the 2.5V supply for numeric and the 2.5V for analog

no other ideas ?

thanks in advance

in my point of view the shape of signal is correct but can't be detected by the PHY chip, because no communication between my prototype and the PC