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Altera_Forum
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15 years ago

Voltage level problem on a pin which is a clock

Hi all, I create this thread because I have a debug problem. On my PCB, my FPGA (EP3C5E144C8N) has to generate a clock to a PHY chip (Marvell 88E1111). With my scope, I can see th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

thanks std_logic_vector

my IO standrd is 2.5V, pin planner proposed me 2.5V or 2.5V(default), I choose 2.5V without suffix

It isn't differential

Vccio of the bank is exactly 2.51V

Any others idea guys ?