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Altera_Forum
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15 years ago

VHDL problem?

QUESTION: Develop a VHDL model for an accumulator that calculates the sum of a sequence of fixed-point numbers. Each input number is signed with 4 pre-binary-point and 12 post-binary-point bits....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The code is very unsynthesisable. The second clock edge is looking for falling edge, and because its inside the rising edge if branch, its basically looking for a rising and falling edge at the same time (so as well as looking for both edges which is impossible in an FPGA, it looks for them simultaneously).