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Altera_Forum
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15 years ago

VHDL problem?

QUESTION: Develop a VHDL model for an accumulator that calculates the sum of a sequence of fixed-point numbers. Each input number is signed with 4 pre-binary-point and 12 post-binary-point bits....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I think when it comes to synthesis we better stick to the proven predictable templates rather than the legality of code. Tools don't always respect the legalities as they are made by low paid software people.

Moreover, the above code will lose the intention as the second edge statement overwrites the first edge.

I believe the intention is DDR, so you can use DDR function or your own.