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Altera_Forum
Honored Contributor
Honored ContributorVHDL problem?
QUESTION: Develop a VHDL model for an accumulator that calculates the sum of a sequence of fixed-point numbers. Each input number is signed with 4 pre-binary-point and 12 post-binary-point bits....
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Ill open a book on how long before he comes back asking why his code wont compile! --- Quote End --- The nested clock edge condidtion compiles, because it's legal VHDL syntax. But the respective part will be ignored similar to a block under an if false then condition. I'll remember it for interview questions.
