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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL problem?

QUESTION: Develop a VHDL model for an accumulator that calculates the sum of a sequence of fixed-point numbers. Each input number is signed with 4 pre-binary-point and 12 post-binary-point bits....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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I have never seen two nested clock edge statements...has vhdl standards changed?

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Ill open a book on how long before he comes back asking why his code wont compile!