VHDL problem?

The problem on this line

acc_out <= q_reg1 + q_reg2;

is that acc_out is 20 bits and q_reg1 and q_reg2 are 16 bits. The result of the addition is 16 bits and it won't be resized automatically to 20 bits for you. Try something like that instead:

acc_out <= resize(q_reg1,20) + resize(q_reg2,20);

It is better to increase the size before performing the addition in case you need the 17th bit in the result and prevent an overflow.

And by the way,

					b_reg(8)  <= b(8);
					b_reg(9)  <= b(9);
					b_reg(10) <= b(10);
					b_reg(11) <= b(11);
					b_reg(12) <= b(12);
					b_reg(13) <= b(13);
					b_reg(14) <= b(14);
					b_reg(15) <= b(15);

can be replaced by

					b_reg(15 downto 8) <= b(15 downto 8);