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Honored ContributorVHDL problem?
QUESTION: Develop a VHDL model for an accumulator that calculates the sum of a sequence of fixed-point numbers. Each input number is signed with 4 pre-binary-point and 12 post-binary-point bits....
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- --this is my code but there are errors.. --the errors are Error (10344): VHDL expression error at acc.vhd(97): expression has 16 elements, but must have 20 elements Error: Can't elaborate top-level user hierarchy Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 2 warnings Error: Peak virtual memory: 183 megabytes Error: Processing ended: Wed Mar 30 08:42:58 2011 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 Error: Quartus II Full Compilation was unsuccessful. 4 errors, 2 warnings
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity acc is
port (
a: in signed (15 downto 0);
b: in signed (15 downto 0);
clk: in std_logic;
ena: in std_logic;
rst: in std_logic;
q: out signed (19 downto 0)
) ;
end acc;
architecture rtl of acc is
signal a_reg, b_reg: signed (15 downto 0);
signal q_reg1, q_reg2: signed (15 downto 0);
signal acc_out: signed (19 downto 0);
begin
process (clk, rst)
begin
if (rst = '1') then
a_reg <= (others => '0');
b_reg <= (others => '0');
q <= (others => '0');
elsif (clk'event and clk = '1') then
a_reg(0) <= a(0);
a_reg(1) <= a(1);
a_reg(2) <= a(2);
a_reg(3) <= a(3);
a_reg(4) <= a(4);
a_reg(5) <= a(5);
a_reg(6) <= a(6);
a_reg(7) <= a(7);
if (clk'event and clk = '0') then
a_reg(8) <= a(8);
a_reg(9) <= a(9);
a_reg(10) <= a(10);
a_reg(11) <= a(11);
a_reg(12) <= a(12);
a_reg(13) <= a(13);
a_reg(14) <= a(14);
a_reg(15) <= a(15);
q_reg1 <= a_reg;
end if;
end if;
end process;
process (ena)
begin
if (ena = '1') then
if (clk'event and clk = '1') then
b_reg(0) <= b(0);
b_reg(1) <= b(1);
b_reg(2) <= b(2);
b_reg(3) <= b(3);
b_reg(4) <= b(4);
b_reg(5) <= b(5);
b_reg(6) <= b(6);
b_reg(7) <= b(7);
end if;
if (clk'event and clk = '0') then
b_reg(8) <= b(8);
b_reg(9) <= b(9);
b_reg(10) <= b(10);
b_reg(11) <= b(11);
b_reg(12) <= b(12);
b_reg(13) <= b(13);
b_reg(14) <= b(14);
b_reg(15) <= b(15);
q_reg2 <= b_reg;
end if;
acc_out <= q_reg1 + q_reg2;
end if;
end process;
q <= acc_out;
end rtl;
