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Altera_Forum
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15 years ago

VHDL problem?

QUESTION: Develop a VHDL model for an accumulator that calculates the sum of a sequence of fixed-point numbers. Each input number is signed with 4 pre-binary-point and 12 post-binary-point bits....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Suppose u r gonna pass out A (4 bits), define another vector for example B (2 bits),

if clock'event and clock='1' then

B(0) <= A(0);

B(1) <= A(1);

end if;

if clock'event and clock='0' then

B(0) <= A(2);

B(1) <= A(3);

end if;