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Altera_Forum
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15 years ago

VHDL Noob question- Recursion?

Hello, I am studying VHDL and am at the topic of signal changes in dataflow and behavior style architectures. So I have two questions. 1) Will the "compiler" ever allow a scenrio where r...
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Altera_Forum
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15 years ago

The construct involves a logic loop rather than recursion. In the present example, the logic loop can either act as a latch or a ring oscillator, depending on the state of signal A.

Apart from the question if the design serves a reasonable purpose, it's basically synthesizable. The compiler will issue a warning about generating a logic loop. The A='1' F='0' ring oscillator case will cause problems in simulation (signal changing every simulation time step) and probably excessive current consumption in hardware.