VHDL Model & Synthesis of Traffic Light Controller

Can someone help me with this, I am getting an error message that says:

"Error (10522): ...experienced unexpected end-of-file ; expecting "begin", or a declaration statement.

here is the code

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity traffic_lights_top is

port(

clk : in STD_LOGIC;

btn : in STD_LOGIC_VECTOR(3 downto 3);

ld : out STD_LOGIC_VECTOR(7 downto 2)

);

end traffic_lights_top;

architecture traffic_lights_top of traffic_lights_top is

component clkdiv is

port(

mclk : in STD_LOGIC;

clr : in STD_LOGIC;

clk190 : out STD_LOGIC;

clk3 : out STD_LOGIC

);

end component;