Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

VHDL integers initialization and FPGAs

I've started coding in VHDL just less than a year ago - unexperienced student warning! My question is about integer initalization. I own an Altera DE1 board and I've also got some experience wi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

OK, thanks a lot for clearing this up :D

I will definitely check out that safe state machine option.

Now I'll try to capture that glitch in SignalTap somehow... I'm not really familiar with state-based trigger flow so I might as well educate myself about it too.