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Altera_Forum
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15 years ago

VHDL integers initialization and FPGAs

I've started coding in VHDL just less than a year ago - unexperienced student warning! My question is about integer initalization. I own an Altera DE1 board and I've also got some experience wi...
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Altera_Forum
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15 years ago

An other point to take care of : I suppose RX is asynchronous to the clock. You should/must not take this asynchronous signal as an input to your state machine. This can cause the described freeze.