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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL integers initialization and FPGAs

I've started coding in VHDL just less than a year ago - unexperienced student warning! My question is about integer initalization. I own an Altera DE1 board and I've also got some experience wi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I simulated using ActiveHDL, so there's no testbench code since I didn't need it. I could write one if you'd like.

Maybe you'd rather like to see simulation results?

Edit: ha, this is interesting. I just tested it again using 'to' instead of 'downto' in the declaration (without the := 0 initialization), and it also worked fine.

So I guess it's a compiler related issue?