Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

VHDL integers initialization and FPGAs

I've started coding in VHDL just less than a year ago - unexperienced student warning! My question is about integer initalization. I own an Altera DE1 board and I've also got some experience wi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

FvM, I'm just used to use downto. No special purpose. I'll try it with 'to'.

Tricky, I have no idea how to capture the exact moment when it freezes.

I have monitored a signal (using SignalTap) which shows when the receiver has a new byte and I saw that after it freezes, that signal never goes up as it should and no new data appears on the data bus.

I have no idea how to capture the exact moment of the glitch.

Maybe you have an idea how to do it using a testbench and/or SignalTap?

By the way thanks for the help and fast replies, guys!